In reading data words from a data storage device for use in a data processing system, it is desirable to determine whether or not the data words, as read out, are the same as the data words which have previously been written into such storage device, i.e., to detect the presence of one or more incorrect data bits therein. Such data storage device, for example, may be a magnetic storage disk onto which a serial data bit stream forming a block of data words has been written, which data words are read out therefrom at a later time.
In conventional error detection circuits, in order to make such a determination the data words which are written onto the disk are accompanied during the "write" mode of operation by an additional error word which has been generated in accordance with a selected polynomial function from the data words which are being stored. During the "read" mode of operation a "read" error word is generated in accordance with a selected polynomial which is equivalent to the "write" polynomial from the data words which are being read out from the storage device. The "write" error word which is then read out from the disk is effectively compared with the "read" error word which is generated during the readout process and, if no error is present in the data words which have been read out, the remainder from an error correction code register utilized for such purpose is zero. If, on the other hand, an error is present, a non-zero remainder is present in the error correction code register. Such non-zero remainder can thereupon be recovered and supplied to the data processing system to signify that one or more errors are present. Such remainder can then be appropriately interpreted for determining the location of and for correcting the errors in accordance with techniques known in the art.
Generally, such error detection circuitry requires relatively complex multiplexing logic and further complex polynomial selection and generation logic requiring a relatively large number of logical elements. Such complexity not only increases the cost of the error detection circuitry but also decreases its reliability. It is desirable, therefore, to simplify as much as possible the error detection circuitry configuration so that hardware complexity and cost considerations can be considerably reduced.